Fuses and anti-fuses have been widely used for over two decades in the semiconductor integrated circuit (IC) industry. Currently, most fuses are of a laser blown fuse type, wherein a metal strip linking two metal contacts is blown (or programmed) by a laser pulse. The state of the fuse--whether blown or not blown--is detected by a latch, and depending on the application, appropriate inferences can be made. The limitations on scaling laser fuses as the IC processing technology continues to shrink the minimum features, the ground rules for circuit design layout that have imposed rigid layout restrictions around the laser fuses, and the introduction of new dielectrics at the back end of the line processing the ICs have all contributed to a migration towards electrically programmable fuses. Electrically programmable fuses come in two versions: fuses and anti-fuses.
An anti-fuse is typically a capacitor having a structure schematically shown in FIG. 1a. A non-conducting dielectric (101) positioned between two conducting plates (102) is depicted. The default state of the anti-fuse is that of the dielectric not electrically conducting. The programmed state is determined by the dielectric electrically conducting. The programmed state can be achieved by applying a voltage sufficiently high to electrically breakdown the dielectric and make it electrically conduct between the two conducting plates (102) of the capacitor. This voltage is called the programming voltage.
During the process of manufacturing an integrated circuit, any capacitor formed with transistor gate-insulators or other in-situ grown oxides or oxy-nitrides may be used as an electrical programmable anti-fuse. In all cases, the conduction of the dielectric in the anti-fuse defines the state of the fuse. However, to be able to implement the electrically programmable anti-fuses in an IC, the programming voltage for the anti-fuse must be contained within the maximum allowable voltage on the IC and, preferably, at its operating voltage.
A MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) can easily be modified to act as an anti-fuse. An electrical circuit equivalent to a MOSFET device is shown in FIG. 1b. The source (103), drain (104) and substrate (105) are electrically connected, forming one end of the conducting plate. The gate (106) provides the second conducting plate. The gate dielectric separating the two plates acts as the insulating layer.
In the present state of the art of growing gate insulators, the electric field required to breakdown (i.e., the intrinsic breakdown field) the gate oxide is greater than 15 mV/cm. This requires that a higher programming voltage be used to breakdown the gate insulator in the electrical antifuse. By way of example, a 3.5 nm thick gate oxide requires in excess of 5 V. to electrically breakdown the oxide. The on-chip voltage is approximately 3.3 V. A lower programming voltage is desirable, especially for programming electrical fuses.
Deep trench (DT) capacitors (FIG. 1c) commonly used in DRAMs may also be used as anti-fuses. They consist of a deep trench (107) having the walls covered with a thin layer of dielectric. The two plates of the capacitor are formed by doped silicon surrounding the DT (108) and by the amorphous silicon within the trench. The plates are electrically contacted from the outside at numerals 109 and 110, respectively.
Various patents related to the fabrication of anti-fuses are listed hereinafter:
U.S. Pat. Nos. 4,757,359 and 5,619,063 describe thin oxides used in an anti-fuse, and formed at the center of the oxide. PA1 U.S. Pat. No. 5,793,094 describes the formation of a thin region anti-fuse below a via hole. It involves a sequence of process steps which differ from the fabrication of MOSFET and MOS capacitors. PA1 U.S. Pat. Nos. 5,502,000 and 5,475,253 describe using corners to obtain lower programming voltages by forming a via in the oxide layer. PA1 U.S. Pat. No. 5,915,171 describes how the bottom conductive layer forming sharp corners is obtained by oxidation and consumption of polysilicon. PA1 U.S. Pat. No. 5,208,177 describes trenching the diffusion region below a dielectric layer. PA1 U.S. Patent Nos. 5,610,084 and 5,486,707 involve implanting nitrogen and argon before growing the oxide dielectric. More particularly, thinner oxides are formed in regions that were implanted prior to the step of growing the oxide. The oxide thickness is primarily responsible for the anti-fuse programming voltage. When used in conjunction with an existing technology, the range of breakdown voltages that can be achieved in the anti-fuse is limited. PA1 (a) Divot fill, wherein the divot is filled with a thinner layer of nitride and the wafer is etched back in a more controlled manner. PA1 (b) Nitride pull-back and oxide pull-back. The sacrificial pad-oxide and nitride that are deposited over the silicon wafer are used to protect the active area during the STI etch. The nitride and/or the oxide layers are pulled back from the edge of the interface between the STI and the active area immediately following the STI etch. This results in rounding the sharp corners at the edges of the active area. Rounded corners exhibit a more uniform growth of the oxide.
Details of the process steps required for fabricating MOSFET and MOS devices can be found in a book by Richard C. Jaeger entitled "Introduction to Micro-electronic Fabrication", vol. 5, with special reference section 1.3, pp. 6-9, "MOS Process Integration".
The formation of shallow trenches referred to in the present invention is described in a book by S. Wolf entitled "Silicon Processing for the VLSI Era", vol. 2--Process Integration", with particular reference to p. 50.
The effect of the formation of corner growth in a silicon wafer and oxide thinning at those corners, described in the invention, is referred to in the above publication by S. Wolf, (p. 55).
MOSFETs and MOS capacitors
The basic mask layout of the basic mask levels for the n-channel MOSFET and MOS capacitor structures are shown with reference to FIGS. 2, 3, 4, and 5, wherein:
The cross-section of the structure formed along the lines AA' (FIG. 2) is shown in FIG. 4.
The cross-section of the structure formed along the lines BB' (FIG. 2) is illustrated in FIG. 5.
The cross-section of the structure formed along the lines CC' (FIG. 3) is also shown in FIG. 5. The cross-sections along the lines BB' and CC' are equivalent to each other.
The fabrication process flow is typical of that used in the manufacture of MOSFET and MOS capacitors, and more particularly, in the fabrication of either p-channel or n-channel MOSFETs.
Referring now to FIGS. 2-4:
Regions 201 (FIG. 2) and 301 (FIG. 3) give rise to metal (i.e., aluminum or copper) levels 407 (FIG. 4) and 504 (FIG. 5).
Regions 202 (FIG. 2) and 303 (FIG. 3) give rise to gate polysilicon region 403 (FIG. 4) and 501 (FIG. 5) on top of the gate dielectric 404 (FIG. 4) and 502 (FIG. 5). The gate oxide thickness in the current technology can be less than 5 nm, and of the polysilicon gate, less than 200 nm.
Regions 203 (FIG. 2) and 302 (FIG. 3) give rise to an active area (AA'). All regions outside this area become the isolation region which in the current technology is by shallow trench isolation (STI).
Regions 204 (FIG. 2) and 304 (FIG. 3) are the contacts to the active area or to the gate poly-silicon and metal level.
Edges 205 (FIG. 2) are the edges of the polysilicon on the gate oxide deposited on the active area. These are referred to in more detail in the schematic cross-section illustrated in FIG. 4 by edges 401 and by the spacers 402 associated with the edges. The spacers are formed by LPCVD (Low Pressure Chemical Vapor Deposition) oxide/nitride, the size depending on the technology being used to fabricate the MOS device. Prior to the formation of the spacers, a lightly doped drain 406 is created by ion implantation. These ions are known to cause damage to the oxide at the edge below the polysilicon. To avoid short channel effects in smaller transistors, n-type dopant ions are implanted just below the lightly doped drain. They are implanted at an angle, a step which is carried out after polysilicon deposition and patterning 403. This implant is referred to as a `halo implantation` 405. Depending on the dose, energy and species of implantation, it is known to cause damage to the oxide which affects its electric breakdown voltage.
Edges 206 (FIG. 2) and 305 (FIG. 3) result in the gate oxide extending to the border of the shallow trench isolation (STI), as shown in 503 (FIG. 5). Corner 306 (FIG. 3) is formed by the intersection of two of the gate oxide STI boundaries. A schematic cross-section of the active area and of the STI prior to the formation of the gate oxide is shown in FIG. 6. Sharp corners of the silicon active area 601 and divots 602 are formed during etch-back of the nitride that define the active area. The sharp corners and the divots can cause the gate oxide grown to become thinner at the edges, as explained in the aforementioned reference by S. Wolf, (p. 50). A thinner oxide is characterized by a lower electrical breakdown voltage.
Since the edges result in a lower breakdown voltage, certain processes are introduced to alleviate the dielectric weakness at the edges. To avoid the sharp corners of the active area at the STI boundary, and divots that result in a thinner and electrically weaker gate oxide growth, steps are taken for rounding the corners and filling the divots. These steps include:
Deep Trench (DT) capacitor anti-fuses
As mentioned earlier, DT capacitors may also be used as anti-fuses (FIG. 1c). In the current technology, trenches (107) 7.5 .mu.m deep and having an aspect ratio greater than 15, are etched into the silicon substrate. The silicon substrate around the trench is doped (108) to form one plate of the DT capacitor. A dielectric is formed on the walls of the DT, typically by either growing oxide or by depositing nitride and further oxidizing it. The dielectric thickness is 5 nm or less. The trench is filled with amorphous silicon.
Objects of the invention
Accordingly, it is an object of the invention to provide an anti-fuse using MOSFET devices or MOS capacitor structures, wherein by varying the implantation dose of indium or other heavy ions prior to the formation of the spacer and after the deposition of the polysilicon for the gate, the programming voltage of the anti-fuse can be varied.
It is another object of the invention to provide an anti-fuse formed using MOSFET devices or MOS capacitor structures, wherein implanting heavy ions, such as indium, on the gate oxide before the polysilicon deposition substantially reduces the programming voltage of the anti-fuse.
It is another object of the present invention to provide an anti-fuse using MOSFET devices or MOS capacitor structures, wherein the mask levels have been modified to enhance weaker spots in the anti-fuse dielectric, making it possible to achieve a lower programming voltage.
It is yet another object of the invention to provide an anti-fuse using MOSFET devices or MOS capacitor structures, wherein a lower programming voltage can be attained by allowing sharp corners and divot s to form at the edge of the active area next to the shallow trench isolation.
It is still another object of the invention to provide an anti-fuse using a deep trench (DT) capacitor structure, wherein the implantation of heavy ions, e.g., indium, in the dielectric node before filling the trench with poly or amorphous silicon reduces the programming voltage.
It is a further object of the invention to provide an antifuse using a DT capacitor structure, wherein by implanting heavy ions in the dielectric node through a thin layer of poly deposited prior to the implantation, results in a lower programming voltage.
It is still a further object of the invention to provide an anti-fuse using DT capacitor structure, wherein the implantation of indium, arsenic, tellurium, and the like into the trench after the first recess etch results in a lower programing voltage of the anti-fuse.